The present invention relates to a level shift circuit for transmitting a signal to a secondary-side system operating with operating potential different from operating potential on the primary side which is the input side.
For example, in a half-bridge circuit in which switching devices are connected in series and which is driven by a high-potential-system power source, a level shift circuit is used for driving high-potential-side switching devices with a low-potential-system signal.
FIG. 19 is a diagram showing a configuration example of a half-bridge circuit using a level shift circuit in the background art. In FIG. 19, the reference numeral 100 represents an output circuit in which switching devices SWL and SWH are connected in series, and to which power is supplied from a high-voltage power source Ein. The switching device SWL is a low-potential-side switching device, which is, for example, an N-channel MOS transistor or an N-type IGBT (Insulated Gate Bipolar Transistor). The switching device SWH is a high-potential-side switching device, which is, for example, an N-channel or P-channel MOS transistor or a P-type or N-type IGBT. Description will be made below in the case where the switching devices SWL and SWH are N-channel MOS transistors.
The reference numeral 110 represents a high-potential-side driving circuit which includes a level shift circuit, a driving device DRVH and a power source E1 (whose output voltage will be hereinafter also designated by the same sign E1). The driving device DRVH performs on/off control on the high-potential-side switching device SWH in response to the output of the level shift circuit. The level shift circuit corresponds to all components of the high-potential-side driving circuit 110 except the driving device DRVH and the power source E1. The level shift circuit includes a series circuit of a resistor R1 (whose resistance value will be also designated by the same sign R1) and an N-channel MOS transistor MN1, a series circuit of a resistor R2 (whose resistance value will be also designated by the same sign R2) and an N-channel MOS transistor MN2, a flip-flop FF serving as a memory device, an inverter (inversion device) INV1 whose input is connected to a first connection point Vsetb (whose potential will be hereinafter also designated by the same sign Vsetb) as a connection point between the resistor R1 and the N-channel MOS transistor MN1 and whose output is connected to a set input terminal S of the flip-flop FF, an inverter INV2 whose input is connected to a second connection point Vrstb (whose potential will be hereinafter also designated by the same sign Vrstb) as a connection point between the resistor R2 and the N-channel MOS transistor MN2 and whose output is connected to a reset input terminal R of the flip-flop FF, and diodes D1 and D2. A signal SH outputted from an output terminal Q of the flip-flop FF is supplied to the driving device DRVH as a signal whose level has been shifted by the level shift circuit. An output of the driving device DRVH is connected to a gate terminal of the switching device SWH. The flip-flop FF, the driving device DRVH and a low-potential-side power supply terminal of the power source E1 are connected to a connection point Vsw (whose potential will be hereinafter also designated by the same sign Vsw) between the switching devices SWL and SWH so that the flip-flop FF and the driving device DRVH can receive power supply from the power source E1. The invertors INV1 and INV2 also receive power supply from the power source E1 in the same manner.
One end of the series circuit of the resistor R1 and the N-channel MOS transistor MN1 and one end of the series circuit of the resistor R2 and the N-channel MOS transistor MN2 are connected to a power supply line Vb (whose potential will be hereinafter also designated by the same sign Vb) which is connected to a high-potential-side terminal of the power source E1, while the other ends thereof are connected to ground potential (GND). Pulse signals PON and POFF, which are input signals to the level shift circuit of the high-potential-side driving circuit 110, are supplied to the gates of the N-channel MOS transistors MN1 and MN2. Anodes of the diodes D1 and D2 are connected to the connection point Vsw between the switching devices SWL and SWH, and cathodes of the diodes D1 and D2 are connected to the first connection point Vsetb and the second connection point Vrstb respectively. The diodes D1 and D2 clamp the input voltages Vsetb and Vrstb to the invertors INV1 and INV2 to prevent the input voltages Vsetb and Vrstb from falling below the potential Vsw and protect the invertors INV1 and INV2 from overvoltage, respectively.
The reference numeral 120 represents a low-potential-side driving circuit which includes a driving device DRVL and a power source E2. The driving device DRVL performs on/off control on the low-potential-side switching device SWL. The driving device DRVL receives power supply from the power source E2, amplifies a signal SL supplied to the driving device DRVL, and supplies the amplified signal SL to a gate terminal of the switching device SWL. With this configuration, the switching device SWL is turned on (continuity) when the signal SL is on an H (High) level, and the switching device SWL is turned off (discontinuity) when the signal SL is on an L (Low) level. That is, the signal SL is a signal which directly gives the switching device SWL an instruction to be on/off.
The input signals PON and POFF supplied to the high-potential-side driving circuit 110 are different from the signal SL. The signal PON is a signal which specifies the start timing of an on period (the end timing of an off period) of the switching device SWH, and the signal POFF is a signal which specifies the start timing of an off period (the end timing of an on period) of the switching device SWH. FIG. 20 shows a timing chart for explaining a level shift operation. When the signal PON is brought into the H level, the N-channel MOS transistor MN1 turns on to bring the potential Vsetb into the L level. The potential Vsetb is inputted to the inverter INV1 to bring the output of the inverter INV1 into the H level. Thus, the flip-flop FF is set to bring the signal SH into the H level to thereby turn on the switching device SWH. On the other hand, when the signal POFF is brought into the H level, the N-channel MOS transistor MN2 turns on to bring the potential Vrstb into the L level. The potential Vrstb is inputted to the inverter INV2 to bring the output of the inverter INV2 into the H level. Thus, the flip-flop FF is reset to bring the signal SH into the L level to thereby turn off the switching device SWH.
Except a dead time when both the switching devices SWL and SWH are off, the switching devices SWL and SWH are turned on/off complementarily (when one is off, the other is on). When the switching device SWL is on, the potential Vsw at the connection point Vsw is equal to the ground potential. When the switching device SWH is on, the potential Vsw at the connection point Vsw is equal to the output voltage of the high-voltage power source Ein (whose output voltage will be also designated by the same sign Ein).
The reference sign RL represents a load for receiving power supply from the half-bridge circuit. The load RL is connected between the connection point Vsw and the ground potential.
Here, consider the case where the switching device SWH turns on in the state where the switching device SWL has been on. On this occasion, the potential Vsw at the connection point Vsw changes suddenly from the ground potential to the high voltage Ein. When the N-channel MOS transistors MN1 and MN2 are off at that time, a false signal called dv/dt noise is overlaid on the connection points Vsetb and Vrstb to set the L level in the both connection points Vsetb and Vrstb shown in FIG. 21 (incidentally, when the N-channel MOS transistors MN1 and MN2 are on, their on states lead to the L level in the connection points Vsetb and Vrstb.). Thus, there arises a problem that a set signal and a reset signal are supplied to the flip-flop FF concurrently to make the output of the flip-flop FF indefinite, that is, a problem that whether the switching device SWH is on or off becomes indefinite. In FIG. 21, the potentials Vsetb and Vrstb before the rising phase of the potential Vsw show the same normal signals as those in FIG. 20. The dv/dt noise will be described below.
A power supply line Vb has potential obtained by adding the constant voltage E1 to the potential Vsw. When the potential Vsw rises, the potential Vb also rises in the same manner (the differential coefficients of the both are equal to each other). That is, this leads to increase in the voltage Vb which should be applied to the series circuit of the resistor R1 and the N-channel MOS transistor MN1 and the series circuit of the resistor R2 and the N-channel MOS transistor MN2. On the other hand, due to parasitic capacitance Cds1, Cds2 between the source and the drain of each N-channel MOS transistor MN1, MN2, change of each potential Vsetb, Vrstb cannot follow the sudden change of the potential Vb. Thus, the difference between the potential Vb and the potential Vsetb, Vrstb becomes larger. In view of each inverter INV1, INV2, this leads to decrease input voltage. This causes the dv/dt noise. Theoretical analysis will be performed on the dv/dt noise below.
FIG. 22 shows a model for analyzing the dv/dt noise. This model includes a series circuit of a resistor R (whose resistance value will be also designated by the same sign R) and a capacitor C (whose capacitance value will be also designated by the same sign C). The series circuit is connected between potential V(t) and ground potential. The resistor R and the capacitor C correspond to each resistor R1, R2 and each parasitic capacitance Cds1, Cds2 shown in FIG. 19 respectively. In addition, the potential V(t) corresponds to the potential Vb. The dv/dt noise becomes a problem when the N-channel MOS transistors MN1 and MN2 are off. In this model, therefore, the channel MOS transistors MN1 and MN2 are regarded as off so as to be ignored. In addition, the diodes D1 and D2 in FIG. 19 are also ignored in this model. Assume that the potential at the connection point between the resistor R and the capacitor C is Vx (which corresponds to the potential Vsetb, Vrstb in FIG. 19), and the initial values of the potentials V(t) and Vx are Vo. Those initial values correspond to a certain steady state where the switching device SWLis on and the switching device SWH is off in the circuit shown in FIG. 19 while the potential Vb and the potential Vx are Vo. The voltage Vo is equal to the potential Vb when the potential Vsw is zero. Therefore, the voltage Vo corresponds to the voltage E1. When those initial values are taken, how the potential Vx changes in response to sudden increase of the potential V(t) is analyzed.
In FIG. 22, a current flowing in the resistor R is integrated by the capacitor C to change the potential Vx. This is expressed by the following Equation (1).
                    Vx        =                  Vo          +                                    1              CR                        ⁢                          ∫                                                (                                                            V                      ⁡                                              (                        t                        )                                                              -                    Vx                                    )                                ⁢                                  ⅆ                  t                                                                                        (        1        )            
When Equation (1) is differentiated, the following Equation (2) can be obtained.
                                          CR            ⁢                                          ⅆ                Vx                                            ⅆ                t                                              +          Vx                =                  V          ⁡                      (            t            )                                              (        2        )            
The suddenly increasing potential V(t) can be expressed by Equation (3), where k is a constant, which corresponds to the time-derivative value of the potential in the power supply line Vb, which is equal to the time-derivative value of the potential Vsw.V(t)=Vo+kt  (3)
When Equation (3) is substituted into Equation (2), the following Equation (4) can be obtained.
                                          CR            ⁢                                          ⅆ                Vx                                            ⅆ                t                                              +          Vx                =                  Vo          +          kt                                    (        4        )            
Equation (4) is a state equation for this model. A general solution of this differential equation can be provided by the following Equation (5).
                    Vx        =                  A          +          kt          +                      B            ×                          exp              ⁡                              (                                  -                                      t                    CR                                                  )                                                                        (        5        )            
In Equation (5), A and B are constants. First, Equation (5) is differentiated to obtain the following Equation (6).
                                          ⅆ            Vx                                ⅆ            t                          =                  k          -                                    (                              B                CR                            )                        ×                          exp              ⁡                              (                                  -                                      t                    CR                                                  )                                                                        (        6        )            
When Equations (5) and (6) are substituted into Equation (4), the following Equation (7) can be obtained.
                                          CR            ⁢                                          ⅆ                Vx                                            ⅆ                t                                              +          Vx                =                              kCR            +            A            +            kT                    =                      Vo            +            kt                                              (        7        )            
From the middle part and the right part of Equation (7), the value of the constant A can be obtained by the following Equation (8)A=Vo−kCR  (8)
When Equation (8) is substituted into Equation (5), the potential Vx can be provided by the following Equation (9).
                    Vx        =                              (                          Vo              -              kCR                        )                    +          kt          +                      B            ×                          exp              ⁡                              (                                  -                                      t                    CR                                                  )                                                                        (        9        )            
Here, the following Equation (10) can be obtained when the aforementioned condition that the initial value of the potential Vx is Vo is substituted into Equation (9).Vx(t=0)=(Vo−kCR)+B=Vo  (10)
Accordingly, the value of the constant B can be provided by the following Equation (11).B=kCR  (11)
When Equation (11) is substituted into Equation (9), the following Equation (12) can be finally obtained for the potential Vx.
                    Vx        =                  Vo          +          kt          -                      kCR            ⁡                          (                              1                -                                  exp                  ⁡                                      (                                          -                                              t                        CR                                                              )                                                              )                                                          (        12        )            
From Equations (3) and (12), the voltage (V(t)−Vx) can be expressed by the following Equation (13).
                                          V            ⁡                          (              t              )                                -          Vx                =                  kCR          ⁡                      (                          1              -                              exp                ⁡                                  (                                      -                                          t                      CR                                                        )                                                      )                                              (        13        )            
Equation (13) is an equation which expresses the magnitude of the dv/dt noise. When the value of the dv/dt noise obtained by Equation (13) increases, the input level to the inverters INV1 and INV2 shown in FIG. 19 becomes L (Low) to invert the outputs of the inverters INV1 and INV2. As is apparent from Equation (13), the larger the constant k is, that is, the sharper the change of the potential Vsw is, the greater the dv/dt noise is. Therefore, the constant k can be regarded as a constant showing the magnitude of the dv/dt noise.
The potential Vb cannot keep increasing without limit as shown in Equation (3). When the potential Vb reaches Ein+E1, the potential Vb stays at that value. FIG. 23 shows a model of the potential V(t) showing the behavior of the potential Vb. In FIG. 23, Vm designates a value corresponding to Ein+E1, and t1 designates the time when the potential V(t) reaches the value Vm. The analysis of the behavior of the potential Vsw after the time t1 when the potential V(t) becomes constant after reaching the value Vm is shown below.
When the value of the potential Vx at the time t1 is V1, Equation (14) is established in the same manner as Equation (1).
                    Vx        =                              V            ⁢                                                  ⁢            1                    +                                    1              CR                        ⁢                          ∫                                                (                                      Vm                    -                    Vx                                    )                                ⁢                                  ⅆ                  t                                                                                        (        14        )            
From this Equation, Equation (15) can be derived in the same manner as Equation (2).
                                          CR            ⁢                                          ⅆ                Vx                                            ⅆ                t                                              +          Vx                =        Vm                            (        15        )            
A general solution of Equation (15) can be provided by the following Equation (16), in which D designates a constant.
                    Vx        =                  Vm          +                      D            ×                          exp              ⁡                              (                                  -                                                            t                      -                                              t                        ⁢                                                                                                  ⁢                        1                                                              CR                                                  )                                                                        (        16        )            
When D is obtained from the initial condition of Vx=V1 at the time t1, the potential Vx can be finally expressed by the following Equation (17).
                    Vx        =                  Vm          -                                    (                              Vm                -                                  V                  ⁢                                                                          ⁢                  1                                            )                        ×                          exp              ⁡                              (                                  -                                                            t                      -                                              t                        ⁢                                                                                                  ⁢                        1                                                              CR                                                  )                                                                        (        17        )            
From this Equation, V(t)−Vx=Vm−Vx for showing the dv/dt noise can be obtained by the following Equation (18).
                              Vm          -          Vx                =                              (                          Vm              -                              V                ⁢                                                                  ⁢                1                                      )                    ×                      exp            ⁡                          (                              -                                                      t                    -                                          t                      ⁢                                                                                          ⁢                      1                                                        CR                                            )                                                          (        18        )            
From Equation (18), it is understood that the dv/dt noise is attenuated in an exponential function of a time constant CR when the potential V (t) is constant.
As described above, the dv/dt noise generated thus leads to a problem such that a set signal and a reset signal are supplied to the flip-flop FF concurrently. Solutions to this problem have been proposed in the background art (for example, Japanese Patent No. 3550453 (FIG. 23)). A background-art half-bridge circuit having a function of preventing malfunction caused by the dv/dt noise as disclosed in Japanese Patent No. 3550453 will be described with reference to FIG. 24. Parts same as those in FIG. 19 are referred to by the same numerals correspondingly, and description thereof will be omitted. FIG. 24 is the same as FIG. 19, except that the diodes D1 and D2 in FIG. 19 are removed, a Zener diode ZD1 and a P-channel MOS transistor MP10 are connected to the resistor R1 in parallel and a Zener diode ZD2 and a P-channel MOS transistor MP20 are connected to the resistor R2 in parallel while the relation of R1>R2 is established. The gate of the P-channel MOS transistor MP10 is connected to the second connection point Vrstb and the gate of the P-channel MOS transistor MP20 is connected to the first connection point Vsetb.
Here, the Zener diodes ZD1 and ZD2 limit input voltages to invertors INV1 and INV2 in place of the diodes D1 and D2. The function of preventing malfunction caused by the dv/dt noise is secured by the relation of R1>R2. That is, the magnitude of the dv/dt noise also depends on the resistance values R1 and R2 as shown in Equation (13). The larger the resistance values are, the greater the dv/dt noise is. Therefore, as shown in FIG. 25, if R1 is set to be larger than R2, the relation of Vsetb<Vrstb can be always established when the dv/dt noise is generated. Thus, the set input surpasses the reset input so that the flip-flop FF can be kept to be set. This is to keep the flip-flop FF set on the assumption that the dv/dt noise is generated only when the potential Vsw increases suddenly, that is, only when the flip-flop FF is set to turn on the high-potential-side switching device SWH. The P-channel MOS transistors MP10 and MP20 are provided for expanding the condition of Vsetb<Vrstb. That is, when the dv/dt noise is generated, each potential Vsetb, Vrstb takes a value as shown in FIG. 25. Accordingly, the on resistance of the P-channel MOS transistor MP10 pulling up the potential Vrstb is made smaller than the on resistance of the P-channel MOS transistor MP20 pulling up the potential Vsetb so that the difference between the potential Vsetb and the potential Vrstb can be expanded.
However, due to resonance generated during soft switching, the dv/dt noise may be generated also when the flip-flop FF has been reset. The aforementioned background-art half-bridge circuit cannot deal with such a phenomenon. Another background-art half-bridge circuit which can deal with such a phenomenon is disclosed in Japanese Patent No. 3550453. FIG. 26 shows the configuration of the half-bridge circuit.
In the circuit shown in FIG. 26, parts same as those in FIG. 24 are referred to by the same numerals correspondingly, and description thereof will be omitted. The circuit in FIG. 26 is the same as the circuit in FIG. 24, except that the gate of the P-channel MOS transistor MP10 is connected to a state-signal output terminal Q of the flip-flop FF and the gate of the P-channel MOS transistor MP20 is connected to a state-signal inverted output terminal QB of the flip-flop FF. In addition, the relation of R1=R2 is established. Due to this configuration, the P-channel MOS transistors MP20 and MP10 are on and off respectively when the flip-flop FF is set to turn on the high-potential-side switching device SWH. Accordingly, the relation of Vsetb<Vrstb is established when the dv/dt noise is generated. Thus, the flip-flop FF can be kept to beset. Accordingly, the high-potential-side switching device SWH can be kept on. In addition, the P-channel MOS transistors MP10 and MP20 are on and off respectively when the flip-flop FF is reset to turn off the high-potential-side switching device SWH. Accordingly, the relation of Vsetb>Vrstb is established when the dv/dt noise is generated. Thus, the flip-flop FF can be kept to be reset. As a result, the high-potential-side switching device SWH can be kept off. That is, whether the high-potential-side switching device SWH is on or off, the on or off state can be kept.
However, in the background-art half-bridge circuit shown in FIG. 26, either the P-channel MOS transistor MP10 or MP20 is always on. In order to invert the state of the flip-flop FF, of the N-channel MOS transistors MN1 and MN2, it is necessary to turn on the N-channel MOS transistor which is connected to the P-channel MOS transistor which is on. Therefore, there is a problem that both the P-channel MOS transistor and the N-channel MOS transistor which are connected between the potential Vb and the ground potential are turned on so that a through current flows therein. In addition, in order to guarantee that the potential Vsetb and the potential Vrstb take the L level for the invertors INV1 and INV2 respectively when the two MOS transistors are on, it is necessary to make the on resistance of each N-channel MOS transistor MN1, MN2 smaller than the on resistance of each P-channel MOS transistor MP10, MP20. The N-channel MOS transistors MN1 and MN2 are high-voltage MOS transistors, whose on resistance is higher than a normal MOS transistor. It is therefore necessary to increase the size (gate width) of the N-channel MOS transistors MN1 and MN2 to decrease their on resistance. Thus, there arises a problem that the through current becomes larger and the semiconductor chip size also increases.
Accordingly, to solve the foregoing problems, an object of the invention is to provide a level shift circuit which can effectively deal with malfunction caused by dv/dt noise regardless of an on or off state of a high-potential-side switching device SWH, while generation of a through current can be suppressed.
Further objects and advantages of the invention will be apparent from the following description of the invention.